A voltage regulation system may offer an efficient mechanism for reducing static power consumption of a memory device (e.g. a static random access memory). When the memory is not accessed for a long period of time, it may switch to an intermediate low-power mode. In this mode, a voltage regulator of the voltage regulation system may be used to reduce the voltage supplied to the memory cells of the memory cell array. The voltage supplied to the memory cells may be a voltage that may be as low as possible, whilst preventing data loss.
Since retention of data in the memory cell array and acceptable levels of static power savings, when the memory is switched into low-power mode, may depend on the voltage supplied to the memory cell array by a voltage regulator, a reliable operation of the voltage regulator should be ensured. Accordingly, there may be a need for adequate test techniques for the voltage regulator. Furthermore, there may be a need to implement such test techniques whilst minimizing chip area. In other words, a test circuit that may be used for the test technique may need to have a low area overhead. Even futher, there may be a need to repair a voltage regulator in case it is determined that the voltage supplied to the memory cell array by the voltage regulator is not in a range of values that may prevent data loss in the memory cell array and that may ensure acceptable levels of static power savings.